ARM ARCHITECHTURE

ARM stands for ADVANCED RISC MACHINES. As the name says it is the group of CPU’S which are based on the RISC Architecture. These ARM Processors are 32-bit and 64-bit RISC multicore processors which are designed to work on small set of computer instructions at higher speeds, performing more millions of instructions per second. RISC Machine provides the better performance than CISC by discarding the unwanted instructions and optimizing pathways.

Use of ARM processors are huge like in consumer electronic devices such as mobiles, mp3 and multimedia players, etc. Its use is increasing day by day due to less complexity, small size, and low power consumption.

ARM Processors are simple designed processors and lead to easy coding and multicore processing.

Features of ARM:

1.      Load/Store Architecture.

2.      Most instructions execute in a single cycle.

3.      Most instructions can be conditionally executed.

4.      Enhanced power-saving design.

5.      64 and 32-bit execution states for scalable high performance.

6.      All instructions are of 32-bit size.

7.      Instruction set extension via coprocessors.

8.      Very dense 16‐bit compressed instruction set (Thumb).

Instructions also extended using the co-processors. It has very dense 16-bit compressed instruction set.

CO-PROCESSORS

ARM consists of up to 16 co-processors defined. These expands the ARM Instruction set. Each Co-processor can have up to 16-private registers of reasonable size. Co-processors are also of type Load-Store Architecture.

There are two states in ARM Architecture.

1. ARM State : When Thumb bit in CPSR is 0
2. Thumb state: When Thumb bit in CPSR is 1.

CPSR is program status register will be explained below.

THUMB

Thumb is a 16-bit instruction set, optimized for code density, improved performance form narrow memory subset of functionality of ARM Instruction set.

Thumb has following features:

1. Most Thumb instructions are executed unconditionally.
2. Many Thumb instructions use 2-address format
3. These are less regular than ARM Instructions formats, leading to dense encoding.

PROCESSOR MODES

There are Six Operating modes in ARM.

USER: Most of the task run under this mode. It is unprivileged mode.

FIQ: Processor enter this mode when the high priority (fast) interrupt is raised.

IRQ: Processor enter this mode when the low priority (normal) interrupt is raised.

Supervisor: Processor enter this mode when a software interrupt instruction is executed.

Abort: This mode entered by processor to handle memory access violations.

Undef: Processor enters this mode to handle undefined instructions.

System: It is introduced as seventh mode after ARMv4, is privileged mode using the same registers as user mode.

REGISTERS

ARM has totally 37 registers. Each of which are 32-bit long.

• 1 dedicated Program Counter
• 1 Current Program Status Register
• 5 Saved Program Status Register
• 30 General Purpose Register

Using the Processor these registers are arranged into several banks. Each mode can access a particular set of r0-r12, r13(stack pointer), r14(link register), r15(program counter) also a cpsr(current program status register), in privileged mode spsr(saved program status register).

Note: system mode uses the User mode Register set.

PROGRAM STATUS REGISTER (CPSR)

Condition Code Flags:

N = Negative result from ALU flag

Z = Zero result from ALU flag

C = ALU operation Carried out

V = ALU operation oVerflowed

Mode Bits:

M[4:0] define the processor mode.

T Bit (Architecture v4T only):

T = 0, Processor in ARM state

T = 1, Processor in Thumb state

Interrupt Disable bits:

I = 1, disables the IRQ

 F= 1, disables the FIQ

                      

PROGRAM COUNTER (R15)

When the processor is executing in ARM state: All instructions are 32 bits in length. All instructions must be word aligned, Therefore the PC value is stored in bits [31:2] with bits [1:0] equal to zero (as instruction cannot be halfword or byte aligned).

R14 is used as the subroutine link register (LR) and stores the return address when Branch with Link operations are performed, calculated from the PC.

Thus to return from a linked branch:

MOV r15, r14

         or

MOV pc, lr

EXCEPTION HANDLING
When an exception occurs, the core:                     

1. Copies CPSR into SPSR_<mode>
2. Sets appropriate CPSR bits If core implements ARM Architecture 4T and is currently in Thumb state, then ARM state is entered.
3. Mode field bits
4. Interrupt disable flags if appropriate
5. Maps in appropriate banked registers
6. Stores the “return address” in LR_<mode>
7. Sets PC to vector address

To return, exception handler needs to:

Restore CPSR from SPSR_<mode> and Restore PC from LR_<mode>.